The invention relates to a latency time circuit for an S-DRAM. D-RAM modules are standard memory modules for main memories. D-RAM memories are composed of large-scale integrated transistors and capacitors. In order to obtain the information, the memory contents must be continuously refreshed in this case. A synchronous D-RAM (S-DRAM) allows memory access without any additional waiting cycles. In this case, the data is transferred between the S-DRAM and an external data bus in synchronism with the external clock signal.
FIG. 1 shows an S-DRAM memory module according to the prior art. The S-DRAM memory module is connected to an external control bus, to an external address bus and to an external data bus. The control commands which are applied to the external control bus are read in via command PADS by means of an integrated command receiver, and the received signals are applied, after signal amplification, to a command decoder. The command decoder decodes the applied control commands which, by way of example, have a length of 4 bits, to form internal control commands, for example write (WR) and read (RD). The S-DRAM contains a state machine or sequence controller which controls the internal sequences as a function of the decoded internal control commands. The sequence controller is clocked by a clock signal. For this purpose, an external clock signal CLKext is applied to the S-DRAM and the signal is amplified by means of an integrated clock signal receiver. The amplified clock signal is distributed in the form of a tree in the integrated S-DRAM by means of a clock tree, and is passed via an internal clock line to a sequence controller. The external clock signal is furthermore applied to a delay locked loop DLL. The delay locked loop DLL causes a negative phase shift in the applied external clock signal CLK. The internal DLL clock signal precedes the external clock signal in order that the data is applied to the data pads in synchronism with the external clock signal. The DLL clock signal DLLCLK is used for clocking the output signal driver OCD (Off Chip Driver), which is integrated in the S-DRAM for one data path. The delay locked loop DLL is followed by a delay element which forms an internal clock signal (VE-CLK) which is modeled such that it is identical to the external clock signal, that is to say VE-CLK is completely in synchronism with CLKext. The delay element for this purpose compensates for the negative phase shift in the delay locked loop DLL.
The internal sequence controller produces control signals for the internal processing sequence of the S-DRAM as a function of the decoded commands. The sequence controller generates an RAS signal (Row Address Strobe) for driving a row address latch, and a CAS signal (Column Address Select) for driving a column address latch. The row address latch and the column address latch are connected via an internal address bus to an address signal receiver for the S-DRAM Via the external address bus, the S-DRAM receives an external address at the address PADS, with the applied address signals being amplified by an address receiver. In order to save connections, the address is entered in DRAM memories in two steps. In a first step, the row address bits are loaded into the row address latch using the RAS signal. In a second step, the column address bits are loaded into the column address latch using the CAS signal. The address bits are applied respectively to a row decoder and column decoder for access to a memory cell within the memory cell array, which is in the form of a matrix. The row address latch and the column address latch as well as the row and column decoders together form an address signal decoder. The sequence controller produces a refresh control signal in order to refresh the memory cells. A refresh counter, which receives this refresh signal from the sequence controller, produces all the existing rows or row addresses successively, which are then applied to the address bus. To do this, the sequence controller produces an RAS control signal. In this way, all the word lines are activated. Activation of a word line results in all the memory cells which are connected to it being refreshed.
The memory cell array is also connected to read/write amplifiers. The number of read/write amplifiers depends on the memory architecture, on the word length and on the prefetch. In the case of a prefetch 4 with a word length of 32, for example, 128 read/write amplifiers are in operation at the same time. If, by way of example, four independent memory banks are provided, a total of 512 read/write amplifiers are integrated on the memory chip.
One data bit is in each case written to an addressed memory cell, or is read from it, via the read/write amplifiers. The read/write amplifiers are connected via an internal data bus to an internal data path in the S-DRAM. The data in the external data bus is written synchronously via the data path to the S-DRAM and is emitted synchronously from the S-DRAM. The data path is connected to the data PADS of the S-DRAM.
In order to read data, the data path has a data receiver for receiving the externally applied data. An internal driver circuit for the data to be written (WR driver) amplifies the signals in the received data and emits the data that has been read via the internal bus to the read/write amplifiers. The driver circuit WR driver is driven by a write/latency time generator, which is clocked by the internal clock generator VE-CLK. The write/latency time generator is itself connected to a decoder.
For synchronous data emission, the data path contains a data FIFO register, which is followed by an output data driver circuit (OCD driver). The FIFO register is driven by the read/write amplifier by means of an input pointer and by a read/latency generator by means of an output pointer or a delayed data enable signal. The read/latency generator is likewise connected to a decoder.
The two decoders for the read latency time generator and for the write latency time generator are connected via internal control lines to a mode register, in which the data for controlling the operating modes is stored within the S-DRAM. The mode register can be initialized by means of a mode register set command via the internal address bus. The mode register is initialized after switch on. Before any external control commands are applied to the S-DRAM, the mode register is initialized. The mode register contains control data for the CAS latency time, for test modes and for DLL reset.
The sequence controller generates an internal write command PAW as a function of the external control commands, in order to activate the write latency time generator, and generates an internal read command PAR for activation of the read latency time generator.
An internal data path control signal PAR/PAW for the read and write latency time generators, respectively, is generated with a certain signal delay, namely for a decoding time xcex94tDEC. This decoding time xcex94tDEC includes a signal delay resulting from the clock signal receiver, the clock signal line tree (clock tree), the downstream latch circuit, resulting from signal delays within the sequence controller, and resulting from signal delay times on the control lines.
tDEK=tCLKRECEIVER+tCLKTREE+tLatch+tCMDDecode+tPARPRODUCTION+tcontrol-line
The generated internal read signal is applied with a short signal delay to the read/write amplifiers, which emit the data to be read out to the internal data bus. The data is passed with a further time delay xcex94tFIFO from the internal data bus via the FIFO register within the data path to the input of the OCD driver. The OCD driver, or data output driver, emits the data with a further signal delay xcex94tOCD to the data PADS of the S-DRAM. There is a delay time xcex94T between the flank of the external clock signal at which the decoded internal read command RD is applied, and the data output via the data PADS.
FIG. 2a shows a latency time generator according to the prior art, which is contained in the data path of the conventional S-DRAM. The conventional latency time generator illustrated in FIG. 2a receives the internal read signal PARint from the sequence controller. The internal read signal is synchronized to the DLL clock by means of a synchronization circuit, which comprises a first synchronization latch A and a second synchronization latch B. The clock signal VE-CLK is completely synchronized to the external clock signal CLK external. In a first step, PAR is synchronized to the VECLK (latch A) and, in a second step, it is synchronized to the DLL-CLK. The internal read signal PARint that has been synchronized in this way is applied to a chain of series-connected time switching elements, each of which causes a delay of one clock cycle. The time switching elements are clocked by the clock signal DLL-CLK. Each of the time switching elements produces a signal delay which is identical to the cycle time of the xcex94tcycle of the external clock signal. cycle
In the read latency time generator as illustrated in FIG. 2a and according to the prior art, the CAS latency time is stored in the mode register, in which case, by way of example, it is possible to store a CAS latency time of 6, a CAS latency time of 5 and a CAS latency time of 4 in the mode register. Memories also exist with other latency times, for example 2, 3 or 7. The read latency time or CAS latency time indicates a number of clock cycles between the application of the external read command and the appearance of the emitted data at the OCD driver. The expression read latency means the number of clock cycles which pass between application of a read command to a synchronous memory and the appearance of the requested data at the output of the memory. A short read latency has the advantage that a connected controller requires fewer waiting cycles. Depending on the lengths of the internal signal delay times, decoding times and amplifier delay times on the memory chip, a short read latency can be achieved, or longer read latency times must be accepted. One important influencing factor in this case is the quality of the production process. These process fluctuations, however, not only govern the read latencies of the memory chip but are also a main influencing factor for the capability of the memory chip to achieve high clock rates.
In order to achieve a read latency time or CAS latency time of CAS=6, the synchronized internal read signal PARint is applied to the chain of timing elements and is delayed with a delay which corresponds to four times the clock cycle time xcex94tcycle. In order to achieve a CAS latency time of 5, the synchronized internal read signal passes through only 3 timing elements, and in order to achieve a CAS latency time of 4, the synchronized internal read signal passes through only 2 timing elements. In a corresponding manner, three inputs are provided on an internal multiplexer for the latency time generator, and are connected to outputs of timing elements within the chain. The decoder decodes the desired CAS latency time, which is stored digitally in the mode register, and drives the multiplexer via a control line. If, for example, a CAS latency time of 4 is stored in the mode register, the decoder connects the third input of the multiplexer to the output control line. The multiplexer is connected on the output side to the FIFO register, and emits a delayed enable signal to the FIFO register.
FIG. 2b shows a timing diagram to explain the function of the latency time generator or latency time counter according to the prior art. The example illustrated in FIG. 2b shows the procedure for a stored CAS latency time of 4. The decoder identifies the CAS latency time of 4, and connects the third input of the multiplexer, so that a time delay is produced by two clocked timing elements. Since the timing elements are clocked by the internal clock signal DLL-CLK, the data is enabled with a time delay after the fourth rising flank of the DLL-CLK clock signal. The internal read command signal which is applied to the latency time generator is in fact passed to the latency time generator only after a time delay of xcex94tDEC.
As the clock frequency of the external clock signal rises, the cycle time tcycle of the clock signal decreases. If the clock rate is 500 MHz, the cycle time tcycle is now only 2 ns, and is in the same order of magnitude as the signal delay times on the chip. Since the time delay xcex94tDEC is constant, a situation occurs when the clock signal frequency is very high in which the signal delay xcex94tDEC is greater than the cycle time tcycle. If the signal delay xcex94tDEC is greater than the cycle time, the signal PAR is synchronized to PARxe2x80x2 with the second VE-CLK signal flank, instead of with the first VE signal flank.
The read latency counter according to the prior art thus switches a very high-frequency applied clock signal one counting clock cycle too late, and the S-DRAM incorrectly emits the data too late. This in turn leads to considerable malfunctions of the overall system, in particular of the microprocessor which is connected to the S-DRAM.
A further fault mechanism, which is independent of this, relates to the offset between VECLK and DLLCLK. If a time offset occurs between DLL-CLK and VE-CLK which is greater than one clock cycle time tcycle, the synchronization of PARint to PARint[sic] occurs with the second DLL-CLK signal flank instead of with the first DLL-CLK flank or, if the first failure mechanism has already occurred, with the DLL-CLK signal flank three of the DLL-CLK flank 2.
FIG. 3a shows the write latency time generator according to the prior art, which is contained in the data path of the conventional S-DRAM. The conventional write latency time generator which is illustrated in FIG. 3b receives an internal data path control signal (PAW) from the sequence controller. A synchronization circuit, which has only one synchronization latch A, synchronizes the internal data path control signal to the VE clock signal. This clock signal VE-CLK is completely synchronized to the external clock signal CLK external. The internal data path control signal, synchronized in this way, is applied to a chain of series-connected time switching elements, which each cause a time delay of one clock cycle. The time switching elements are clocked by the clock signal VE-CLK. Each of the time switching elements produces a signal delay which is identical to the cycle time of the xcex94tcycle of the external clock signal.
In the write latency time generator as illustrated in Figure and according to the prior art, the CAS latency time is stored in the mode register, in which case, for example, CAS latency time of 6, a CAS latency time of 5 and a CAS latency time of 4 can be stored in the mode register. Memories also exist with other latency times, such as 2, 3 or 7.
The read latency time or CAS latency time indicates the number of clock cycles between the application of the external read command and the appearance of the output data at the OCD driver. A low read latency CAS has the advantage that a connected controller requires fewer waiting cycles. A short read latency CAS can be achieved, or longer read latency times must be accepted, depending on the length of the internal signal delay times, decoding times, and amplifier delay times on the memory chip. One important influencing factor in this case is the quality of the production process. However, these process fluctuations govern not only the read latencies CAS of the memory chip, but are also a main influencing factor for the capability of the memory chip to achieve high clock rates.
The expression write latency means the number of clock cycles which pass between the application of a write command and the application of the data to the inputs of the memory chip. The read latency time CAS for conventional S-DRAMs can be programmed into a mode register. The write latency in the case of the DDR2 Standard is coupled to the read latency CAS and is one clock cycle less than the read latency.
Write latency=read latencyxe2x88x921.
As can be seen from FIG. 3a, a CAS latency of 4 corresponds to a write latency of 3, and to a time delay of 2xcex94tcycle by means of two timing elements of the write latency time generator.
FIG. 3b shows a writing process for an S-DRAM with a stored CAS latency time of 4. A write command WRITE is applied and is decoded during the clock cycle 0 of the external clock signal. The sequence controller generates an internal time control signal, which is generated with a certain signal delay, namely with the decoding time xcex94tDEC. This decoding time includes a signal delay resulting from the clock signal receiver, the clock signal line tree, the command decoding and resulting from signal delays within the sequence controller. As the clock frequency of the external clock signal rises, the cycle time tcycle of the clock signal decreases. Since the time delay xcex94tDEC is constant, a situation occurs with a very high-frequency clock signal in which the signal time delay xcex94tDEC is greater than the cycle time tcycle. In this situation, the PAW control signal can no longer be received with the signal flank 1 of the VE-CLK as illustrated in FIG. 4b, but only with the signal flank 2 of the VE-CLK clock signal. This means that the synchronization of the internal write signal PAW to PAWxe2x80x2 by means of the synchronization circuit within the write latency time generator incorrectly takes place delayed by one entire signal clock cycle, that is to say with the signal clock cycle 2 instead of with the signal clock cycle 1. If the clock cycle time thus decreases as a result of an excessively high clock frequency into the time region of the decoding time, then there is no longer any guarantee that the write data path within the S-DRAM will be switched on in a stable manner.
In order to avoid the malfunction as described above of the write latency circuit according to the prior art, attempts have already been made to minimize the signal delay times, in order to reduce the delay time xcex94tDEC.
However, at very high clock frequencies, minimizing the signal delay times reaches its limits, and is no longer sufficient to prevent a malfunction.
The object of the present invention is thus to provide a latency time circuit for an S-DRAM which operates in a fault-free manner even with a very high-frequency clock signal, that is to say it emits a data enable signal with the desired latency time to the data path.
This object is achieved by a latency time circuit having the features described herein.
The invention provides a latency time circuit for an S-DRAM which is clocked by a high frequency clock signal, for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM having: at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, wherein at least one comparison circuit, which compares the cycle time of the high-frequency data signal with a predetermined decoding time and having a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.
In one preferred embodiment of the latency time circuit according to the invention, the comparison circuit reduces the latency time, which is generated by the latency time generator, by one cycle time when the cycle time of the clock signal is in the limit time region.
In one preferred embodiment of the latency time circuit according to the invention, the comparison circuit reduces the latency time which is generated by the latency time generator by one cycle time when the cycle time of the clock signal is in a critical time region below the limit time region.
A mode register is preferably provided for storing a programmable latency time.
Furthermore, a decoder is preferably provided, which decodes the programmed latency time CAS in order to produce an internal control signal for the latency time generator.
The comparison circuit preferably emits a correction control signal to the decoder when the cycle time of the clock signal is in the limit time region or in the critical time region.
The controllable latency time generator preferably has a number of series-connected time switching elements, which each pass on a signal which is applied to a signal input to their signal output, delayed by the cycle time.
The signal outputs of the time switching elements are in this case each connected to one signal input of a controllable multiplexer within the latency time generator.
The multiplexer preferably has a control input for the internal control signal which is emitted by the decoder.
The signal delay of all the series-connected time switching elements is preferably equal to a maximum programmable latency time minus two.
In the absence of the correction indication control signal, the decoder drives the multiplexer such that the signal delay which is produced by the time switching elements is equal to the programmable latency time reduced by two cycle times.
On receiving the correction indication control signal, the decoder preferably furthermore drives the multiplexer such that the signal delay produced by the time switching elements is reduced by one cycle time.
The latency time generator of the latency time circuit according to the invention preferably has a synchronization circuit for synchronization of the decoded data enable control signal to an internal clock signal.
In one particularly preferred embodiment of the latency time circuit according to the invention, the comparison circuit preferably has a test signal generator for producing a test signal; a delay circuit, which comprises at least one series-connected delay element, for delaying the test signal which is produced, a clocked clock pulse generator for producing a clock pulse whose pulse duration is equal to the cycle time of the clock signal, at least one associated transfer gate circuit with an input for application of the delayed test signal, a clock input for application of the clocked clock signal and having an output to which the delayed test signal which is produced is passed on when the delay time of the delay circuit is shorter than the pulse duration of the clock pulse which is produced by the clock pulse generator, and a latch circuit for temporary storage of the passed-on delayed test signal, in which one signal output of a delay element is in each case connected through an associated transfer gate circuit to a latch circuit.
The test signal is preferably a logic-high signal pulse with a long pulse duration.
The test signal which is preferably passed on is temporarily stored as a correction indication bit in the latch circuit.
The delay circuit preferably comprises a first delay element having a first signal delay time, and a series-connected second delay element having a second signal delay time, with the sum of the two signal delay times being equal to the predetermined decoding time.
The delay circuit preferably has a third delay element with a third signal delay time, with the third signal delay time being equal to the difference between the predetermined decoding time and the first signal delay time.
The comparison circuit preferably and additionally has a logic circuit, which logically links the temporarily stored correction indication bits to the first correction control signal in order to drive a multiplexer, and to the second correction control signal in order to drive the decoder.
After receiving an enable signal from the internal sequence controller of the S-DRAM, the test signal generator preferably produces the test signal.
Preferred embodiments of the latency time circuit according to the invention will be described in the following text with reference to the attached figures in order to explain features which are significant to the invention.